The present disclosure relates to semiconductor devices and manufacturing methods thereof, and more particularly to semiconductor devices to which a high voltage is applied, and manufacturing methods thereof.
As electronic apparatuses have been increasingly reduced in size and weight and increased in performance, semiconductor packages that are mounted in the electronic apparatuses have been required to be reduced in size, thickness, and weight in order to implement high-density mounting on mount substrates. A semiconductor package technique called “chip scale package (CSP)” has been developed in order to reduce the size of the semiconductor packages. In the CSP, a sealing step is completed in a wafer state, and the size of semiconductor packages is the same as or slightly larger than that of individual chips separated by dicing. A semiconductor chip for the CSP has its surface covered by a protective film, and has a polyimide layer or a redistribution layer formed on the protective film, and a surface-side resin layer that seals the redistribution layer, etc. A plurality of external terminals electrically connected to the semiconductor chip are provided over the surface-side resin layer. The external terminals are bonded to lands on a mount substrate to mount the semiconductor chip on the mount substrate.
The CSP has also been applied to power transistors for power supply circuits, etc. in order to reduce the size. For example, the following semiconductor device using the CSP is known in the art (see, e.g., Japanese Patent Publication No. 2005-354105). As shown in FIG. 12, in a conventional semiconductor device, a semiconductor chip 30 separated by dicing is sealed and accommodated in a recess of a metal frame 100 by using an epoxy resin 103. The semiconductor chip 30 has a solderable contact layer 40 on a first surface thereof, and a second surface of the semiconductor chip 30 serves as a drain electrode. The drain electrode of the chip is bonded to a bottom surface 101 of the recess of the metal frame 100 by solder 102, and the upper surface of the contact layer 40 is flush with a protruding portion 105 of the metal frame 100. Thus, the contact layer 40 and the protruding portion 105 can be connected to a contact of a mount substrate. With this configuration, a power metal oxide semiconductor (MOS) device can be compactly mounted.